Location: EE 045
Intel PhD Tech Talk:
Intel’s Silicon process technology with an emphasis on scaling electronic devices
Join David Clifton, Florentina Perjeru, and Todd Schmidt for a discussion on Intel’s Silicon process technology with an emphasis on scaling electronic devices.
David Clifton is currently the Chemical Mechanical Planarization and Plating Manager in Logic Technology Development. He joined Intel in 1993 as a Process Engineer and has since worked on CMP processes at various technology nodes. He currently manages the CMP and Plating groups that are responsible for ramping Intel’s next generation technologies from development to high volume.
Florentina Perjeru has received her PhD in Semiconductor Physics from Ohio University. She joined Intel in 2001 as Lithography Process Engineer and has held various technical and manager roles spanning the last seven technologies transfers and high volume manufacturing. Currently she is the Yield Manager, responsible for IMO RA startup, which is the latest addition to the manufacturing environment in Hillsboro. Throughout her career as a manager, Dr Perjeru has mentored numerous new hires and has been at the forefront of diversity efforts, including owning the Technical Females Initiative efforts for IMO RA organization.
Todd Schmidt joined intel in 1996. He has worked on Intel technologies from 350 nm to today’s current leading edge 14nm technologies. He’s currently a dry etch manager in Intel’s D1C factory in Hillsboro Oregon. He has worked in planarization, metallization, dielectrics and dry etch
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