Please email resume and optionally a cover letter to David Wadkins at David.Wadkins@synopsys.com. Note: Synopsys has offices in many locations, so hiring location may not necessarily mean you must move there.
CAD Engineer, Sr II
Requisition Number 2478BR
Hiring Location(s) USA - California - Mountain View/Sunnyvale
Job Category Engineering
Business Unit SG, Administration
Hire Type Employee
Recruiter Mona Knutsen
Hiring Manager (Reports To) Weikai Sun
Grade 67
Job Description and Requirements Sr. CAD engineer responsible for operation and activities of CAD in Analog, Mixed-Signal design flow. The primary responsibilities include interfacing with various foundries to get Process Design Kits (PDK) installed, customized, QAed, and released; supporting Synopsys Embeded Memory design infrastructure; transistor level simulation support; and various backend verification support (DRC/LVS, parasitic extraction, EMIR analysis, etc.).
Qualifications include
· Has a strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills.
· Must have transistor level simulations experience, including hands-on experience with major EMIR analysis tools
· Must have hands-on experience with shell scripting and other programming skills such as TCL/Perl for flow automations.
· Experience in deep-submicron CMOS technology and IP/product development
· Experience in working with foundries in a fabless semiconductor product development model
· BS in CS/EE with 6+ years of relevant experience, MS with 3+ years of relevant experience. Requires prior cad tool development experience.
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Business Title Analog & Mixed Signal Design Engineer
Requisition Number 567BR
Hiring Location(s) CANADA - Ontario - Mississauga
Job Category Engineering
Business Unit SG, Intellectual Property
Hire Type Employee
Recruiter Andrea Timlin
Hiring Manager (Reports To) Michael Lynch
Grade 66
Job Description and Requirements
Responsible for designing analog, RF and mixed-signal integrated circuits. Develops circuit specifications working from published protocols and standards. Selects/creates circuit architectures based on practical experience and knowledge of current circuit literature. Applies theoretical knowledge to analyze and explain circuit behavior and limitations. Implements rigorous simulation test-benches to verify circuit performance. Incorporates test and tuning controls. Participates in critical peer reviews. Clearly documents all circuit details. Guides, implements and reviews IC layouts.
Requires a BSc in Electrical or Computer Engineering with 5+ years of experience, or MSc with 3+ years of experience, or PhD with 1+ years of experience. Possesses a solid understanding of specialization area plus working knowledge of one other related area. Resolves issues in creative ways. Exercises judgment in selecting methods and techniques to obtain solutions. Execute projects from start to completion. Contributes to moderately complex aspects of a project. Receives little instructions on day-to-day work, general instructions on new assignments and projects. Determines and develops recommendations to solutions. Work is evaluated upon completion to ensure objectives have been met. Works on team-driven or task-oriented projects. May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise.
You will be part of an R&D team developing high speed analog integrated circuits. We are looking for an engineer with theoretical knowledge and practical experience to contribute to the team. Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You must have experience in designing at least two of the following key functions: Clock and Data Recovery, PLLs, Transmitters, Receivers, Bandgaps. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team. Experience with tools for schematic entry, IC layout and SPICE simulation is required. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture. Experience with TCL, perl, C, python, MATLAB, or other scripting languages is desired.
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Business Title R&D Engineer, Sr II
Requisition Number 2491BR
Hiring Location(s) USA - Washington - Seattle
Job Category Engineering
Hire Type Employee
Recruiter Beth Nguyen
Hiring Manager (Reports To) Beth Nguyen
Grade 67
Job Description and Requirements Design, develop and test electronic circuits, components, and systems utilizing knowledge of electronic theory, materials properties, and EDA tools. Determine hardware compatibility and/or influence hardware design. Work on problems of diverse scope where analysis of data requires evaluation of various factors where assignments are given in the form of objectives. Analyze project areas, refine problem descriptions, and develop novel technical solutions. Write papers for technical conferences.
Requires Master’s degree in Computer Engineering, Electrical/Electronic Engineering, Computer Science or a related field and two years of experience in mixed signal ASIC design and verification. Must also have background in: 1) define RTL’s using Verilog; 2) RTL synthesis/writing timing constraints; 3) writing and executing verification plans at block + chip-level; 4) static timing analysis of asynchronous designs; 5) mixed signal design; 6) automation of design flow using scripting; 7) .lib model creation/validation; and 8) ASIC design flow.
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Business Title R&D Engineer, Sr II
Requisition Number 2492BR
Hiring Location(s) USA - Washington - Seattle
Job Category Engineering
Hire Type Employee
Recruiter Beth Nguyen
Hiring Manager (Reports To) Beth Nguyen
Grade 67
Job Description and Requirements Develop custom PDK’s for non-volatile memory IP to be integrated into SoC’s. Determine hardware compatibility and/or influence hardware design. Determine hardware compatibility and/or influence hardware design. Work on problems of diverse scope where analysis of data requires evaluation of various factors where assignments are given in the form of objectives. Analyze project areas, refine problem descriptions, and develop novel technical solutions. Write papers for technical conferences.
Requires Master’s degree in Computer Engineering, Electrical/Electronic Engineering, Computer Science or a related field and two years of experience in PDK development. Must also have background in: 1) customizing CAD tools for PDK development; 2) developing physical verification rule decks; 3) creating Pcells; 4) SKILL, C++, scripting languages; 5) UNIX; and 6) CVS.
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Business Title R&D Engineer, Sr II
Requisition Number 2328BR
Hiring Location(s) USA - Oregon - Hillsboro
Job Category Engineering
Hire Type Employee
Recruiter Beth Nguyen
Hiring Manager (Reports To) Beth Nguyen
Grade 67
Job Description and Requirements Design, develop, or test EDA or DFM tools used to design electronic circuits, components, and systems utilizing knowledge of electronic theory, materials properties, and/or EDA tool development. Determine hardware compatibility and/or influences hardware design. Work on problems of diverse scope where analysis of data requires evaluation of various factors where assignments are given in the form of objectives. Analyze project areas, refine problem descriptions, and develop novel technical solutions. Design and implement sophisticated algorithms to solve complex problems. Write papers for technical conferences.
Requires Master’s degree in Computer Engineering, Electrical/Electronic Engineering, Computer Science or a related field and two years of experience in a relevant position. Must also have experience or background in data structures/algorithm design; compiler and compiler backend technology; Verilog and HDL simulation technology; performance analysis and profiler tools using SKILL; time profiler and memory profiler development; ASIC design flow; and appropriate tools and programming languages.
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Business Title Software Engineer, Sr II
Requisition Number 1385BR
Hiring Location(s) USA - California - Mountain View/Sunnyvale
Job Category Engineering
Business Unit Verification Group
Hire Type Employee
Recruiter Doug Paxman
Hiring Manager (Reports To) Claudio Basile
Grade 67
Job Description and Requirements
The Verification Group (VG) at Synopsys is responsible for researching, developing, and deploying innovative technologies that enable our customers to verify their hardware designs with greater accuracy and speed. Because of the size and complexity of our customer designs, writing fast and efficient code is a major part of our job. But performance at any cost (i.e. code complexity) is a short-sighted goal. Thus we place a very high emphasis on code quality, and we enforce this with automatic and peer-enforced coding guidelines, design/code reviews, and Agile practices like test-driven development.
This particular position is on a team that, while fully integrated with the larger VG organization, operates much like a small company would. We benefit from “big company” resources provided by the VG organization and Synopsys as a whole, but we move at the speed of a startup. As such, we value independent thinkers who like to solve challenging problems by growing and leveraging their own skills while involving domain experts in the problem solving process as needed. If you are the type of developer that doesn’t let any technical issue stand in your way, then this is the team for you.
An exciting opportunity to be part a small and highly focused team working on a disruptive technology for hardware design verification. Looking for an energetic and self-motivated candidate with good communication skills, strong background in software development, and familiarity with hardware design.
Required:
- Strong familiarity with C++ (STL, design patterns, Boost library), data structures, and algorithms
- Familiarity with Linux.
- BS in CS, EE, or ECE, or equivalent experience.
Preferred:
- Familiarity with hardware design.
- Familiarity with EDA algorithms for logic simulation and verification
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Business Title R&D Engineer, Sr II
Requisition Number 1684BR
Hiring Location(s) USA - California - Mountain View/Sunnyvale
Job Category Engineering
Business Unit SG, Administration
Hire Type Employee
Recruiter Jeff Vise
Hiring Manager (Reports To) Mitesh Shah
Grade 67
Job Description and Requirements
We are a team working on producing the highly optimized compiler toolchain for ARC family of 32-bit configurable processors. We are looking for an engineer like you to be part of the team to work on a world-class highly optimizing compiler toolchain that produces very fast and tight code to help customers develop very sophisticated embedded applications.
Responsibilities:
· Develop and implement ARC core specific optimizations in the compiler backend
· Maintain and enhance the current set of ARC compiler tools
· Interact with Hardware architects and other teams and provide compiler tools perspective for the processor design as well as applications design
· Perform various benchmarking and engineering testing tasks to improve the quality of the compiler products
· Assist product marketing and product support teams with pre and post sales situations as needed
Qualifications:
· Minimum of 5+ years of related experience
· Thorough understanding of the compiler and other related development tools internals
· Extensive knowledge and experience with the compiler development
· Knowledge of compiler backend technologies such as register allocation, instruction scheduling, loop transformations, peephole optimizations, etc
· Expert-level programming skills in C, C++ and assembly languages
· Expert-level design, coding and debugging skills
· Knowledge of ARC processors and ISA is a plus
· Experience with the implementation of embedded processor development tools is desirable
· Experience with the development tools such as SVN and Bugzilla
· LLVM system experience a plus
· Excellent teamwork and communication skills
· BSCS degree or equivalent, MSCS preferred
